```{toctree}
---
maxdepth: 2
hidden: true
---



docs/src/architecture.md

docs/src/cli.md

docs/src/api.md

docs/src/amaranth.md

docs/src/verilog.md

docs/src/cocotb.md


```

# dau sim

dau simulator

[![Build Status](https://github.com/dau-dev/dau-sim/actions/workflows/build.yaml/badge.svg?branch=main&event=push)](https://github.com/dau-dev/dau-sim/actions/workflows/build.yaml)
[![codecov](https://codecov.io/gh/dau-dev/dau-sim/branch/main/graph/badge.svg)](https://codecov.io/gh/dau-dev/dau-sim)
[![License](https://img.shields.io/github/license/dau-dev/dau-sim)](https://github.com/dau-dev/dau-sim)
[![PyPI](https://img.shields.io/pypi/v/dau-sim.svg)](https://pypi.python.org/pypi/dau-sim)

## Overview

dau-sim simulates digital hardware designs using [csp](https://github.com/Point72/csp)'s reactive stream processing engine. Hardware signals become CSP time-series edges, combinational logic becomes CSP nodes, and clock domains become CSP clock processes — giving you cycle-accurate simulation with deterministic event scheduling and multi-clock support.

**Supported inputs:**

- [Amaranth HDL](https://amaranth-lang.org/) — Python-native hardware description
- [SystemVerilog / Verilog](https://www.systemverilog.io/) — via [pyslang](https://github.com/MikePopoloski/pyslang)
- Hand-constructed IR — for programmatic design generation

**Output formats:** VCD (IEEE 1364-2001) waveform files, with FST and live streaming planned.

## Installation

```bash
pip install dau-sim
```

For development:

```bash
git clone https://github.com/dau-dev/dau-sim.git
cd dau-sim
pip install -e ".[develop]"
```

## Quick Start

```python
from amaranth.lib import wiring
from amaranth.lib.wiring import In, Out
from amaranth.hdl import Module

from dau_sim.frontends import from_amaranth
from dau_sim.compiler import compile_module


class Counter(wiring.Component):
    en: In(1)
    count: Out(8)

    def elaborate(self, platform):
        m = Module()
        with m.If(self.en):
            m.d.sync += self.count.eq(self.count + 1)
        return m


cm = compile_module(from_amaranth(Counter()))
traces = cm.run(cycles=20, inputs={"en": 1})
cm.write_vcd("counter.vcd", traces)
```

## Documentation

| Topic                                          | Description                                |
| ---------------------------------------------- | ------------------------------------------ |
| [Amaranth](docs/src/amaranth.md)               | Simulating Amaranth HDL designs            |
| [Verilog / SystemVerilog](docs/src/verilog.md) | Simulating SV/V designs and hand-built IR  |
| [cocotb](docs/src/cocotb.md)                   | Running cocotb testbenches against dau-sim |
| [CLI](docs/src/cli.md)                         | Command-line interface reference           |
| [Architecture](docs/src/architecture.md)       | Pipeline and internal design               |
| [API Reference](docs/src/api.md)               | Full API tables                            |
| [Benchmarks](docs/src/benchmarks.md)           | Performance numbers and execution modes    |

## License

This project is licensed under the Apache 2.0 License — see [LICENSE](LICENSE) for details.